This book offers the first comprehensive coverage of digital design techniques to expand the power-performance tradeoff well beyond that allowed by conventional wide voltage scaling.  Compared to conventional fixed designs, the approach described in this book makes digital circuits more versatile and adaptive, allowing simultaneous optimization at both ends of the power-performance spectrum. Drop-in solutions for fully automated and low-effort design based on commercial CAD tools are discussed extensively for processors, accelerators and on-chip memories, and are applicable to prominent applications (e.g., IoT, AI, wearables, biomedical). Through the higher power-performance versatility techniques described in this book, readers are enabled to reduce the design effort through reuse of the same digital design instance, across a wide range of applications.  All concepts the authors discuss are demonstrated by dedicated testchip designs and experimental results. To make the results immediately usable by the reader, all the scripts necessary to create automated design flows based on commercial tools are provided and explained.

Saurabh Jain received the bachelors and masters degrees from Indian Institute of Technology, Kanpur, India, in 2012 and 2013 respectively, the Ph.D. degree from National University of Singapore, Singapore, in 2018. After his Ph.D. he worked as a postdoctoral research fellow at the Department of Electrical and Computer Engineering of the National University of Singapore. Currently he is working as a research scientist at the processor architecture research lab (PARL) at Intel Labs, Bangalore.

His research interest includes development of reconfigurable architectures for widely voltage-scalable memory and logic and general purpose compute-in-memory.

Longyang Lin received the dual bachelor's degrees from Shenzhen University, Shenzhen, China and Umeå University, Umeå, Sweden, in 2011 and the master's degree from Lund University, Lund, Sweden, in 2013, and the Ph.D. degree from the National University of Singapore, Singapore, in 2018. He is currently a postdoctoral research fellow at the Department of Electrical and Computer Engineering of the National University of Singapore.

His research interests include ultra-low power VLSI circuits, self-powered sensor nodes, widely energy-scalable VLSI circuits and general purpose compute-in-memory.

Massimo Alioto received the Laurea (MSc) degree in Electronics Engineering and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001, and the Bachelor of Music in Jazz Studies from the Conservatory of Music of Bologna in 2007. He is with the Department of Electrical and Computer Engineering, National University of Singapore where he leads the Green IC group and is the Director of the Integrated Circuits and Embedded Systems area. Previously, he held positions at the University of Siena, Intel Labs CRL (2013), University of Michigan Ann Arbor (2011-2012), BWRC University of California, Berkeley (2009-2011), and EPFL (Switzerland, 2007).

He has authored or co-authored more than 280 publications on journals and conference proceedings. He is co-author of four books, includingEnabling the Internet of Things - from Circuits to Systems(Springer, 2017),Flip-Flop Design in Nanometer CMOS - from High Speed to Low Energy (Springer, 2015), andModel and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits(Springer, 2005). His primary research interests include self-powered wireless integrated systems, near-threshold circuits for green computing, widely energy- scalable and energy-quality scalable integrated systems, data-driven integrated systems, hardware-level security, and emerging technologies, among the others.

Introduction to wide voltage scaling, applications and challenges.- Reconfigurable microarchitectures down to pipestage and memory bank level.- Automated design flows and run-time optimization for reconfigurable microarchitectures.- Case studies of reconfigurable microarchitectures: accelerators, microprocessors and memories.- Reconfigurable clock networks, automated design flows, run-time optimization and case study.- Conclusion.